How is the dual-channel memory mode implemented in the memory controller (architecturally/logically/circuitry)?

Question

Electronics

I wonder what the memory controller is in modern PCs.
From what is clear - how the operative works - an address is sent to the address bus - a cell is sampled - from the cell from each bit its state is fed to the pins / lines of the data bus.
The bar has a maximum speed of the elements - hence the frequency limit.
Now I'm interested in how the two-channel mode is implemented in electronics architecturally (at the level of approximately circuitry).
As I understand it, whenever possible, they try to interrogate alternately one channel, then another, as a result, externally, the memory access frequency is theoretically x2.
But how is it solved if memory cells on the same channel are polled in two adjacent cycles - the bar cannot work above its frequency. Is he just waiting?
PS: Google only gives out articles at the level of how a student can put memory sticks in his PeKa so that there is a two-channel mode XD

Answer 1

2-channel mode is the simultaneous polling in 2 places.
In the most ideal case, the access speed is maximum when the request goes to different physical bars, it is clear that each bar with its own controller is occupied only with its own data.
But it often happens that the request goes to one bar, then you have to wait - so single-channel.
To solve this situation, there is an access algorithm, when addresses and operations from the processor are put into a buffer, and from there the memory controller divides the addresses into strips, if it can.
Schematically, instead of the old single-channel controller, a heavier controller appears on the bus between the processor and memory sticks, with which the stick controllers communicate as if they were communicating via one channel. An address distribution block and a second buffer appear in the controller, probably. Roughly speaking, the address from the processor simply selects which bar to "interrupt". And the apparent simultaneity of requests is achieved due to the access pipeline in the memory strips.
Sampling from memory occurs in whole blocks - they give the starting address, length and operation, then all this is sent to the bus, then they read or write data via interrupts without specifying the address. The memory strips have their own pipeline, which independently processes requests. Since reading on the bus is faster than reading from cells, you still have to wait for some time, but the bus is freed.
_{So I think.}

Answer 2

Nothing happens, everyone is waiting.