Synthesis of logic circuits on Verilog?

Question

Circuit design

I want to design a simple circuit in Verilog. For such trifles, FPGAs are too expensive to buy, and there are many nutritional problems. Is it possible to synthesize Verilog code into a graphical logic / transistor connection diagram, so that later I can assemble it all by hand?

Answer 1

In logical elements for "Quartus 20.1 Lite Edition" Tools > Netlist Viewers > RTL Viewer.
P.S. The EPM240 is inexpensive and replaces 100 - 200 simple logic ICs, works great from 3.3V.