How is it more convenient to present the logical description of the FPGA?

Question

Electronics

Let's say you have some FPGA (Altera or Xilinx) and the ability to download the firmware for analysis in order to know what kind of logic is implemented inside.
In what form would such information be most useful? A graphical representation of logical elements and connections between them, in one of the descriptive languages ​​(Verilog, VHDL), a timing diagram, something else?

Answer 1

Structural diagram, and then a logical diagram, and then already VHDL.

Answer 2

The block diagram is of course good, but it will only be if there is a description for the project.
Usually everything is limited to HDL code (VHDL or Verilog HDL) and test benches that form time diagrams of work and some kind of report. Taking on a job where there is a complex, undocumented code is a very unrewarding task, it is rather difficult to trace an idea through the HDL code. It is better to avoid such jobs where someone has gained something 10 years ago and this needs to be dealt with.