How does the processor understand the command?

Question

Processors

I am reading the book "Code. The Secret Language of Informatics". There was such a question. In chapter 17, the author shows a simple diagram of a computer, and how it works. So in that example, the processor received a command, for example (load / add / save) in binary form. As I understand it, this is how the intel 8080 worked. I can’t understand how the processor understands the load command (for example, 0000001), that is, how does it understand what it needs to do specifically? These commands are set physically and then somehow compared?

Answer 1

Well, if it's simple, then delving into the examination of the microprocessor, we will see that at the very "bottom" is the so-called "Elements of digital logic" "AND, OR, NOT".
These are LEGO bricks from which everything is assembled. These are the atoms of all digital technology.
So if we say we put 8 elements in parallel and apply 8 signals to them (with some kind of logical level 0 or 1 - "00101001" then at the output we will get 8 response signals (depending on which element is in this position "101011100") Well ,
this sequence of LEGO cubes determines the processor command system (for example, x86, or ARM .....) and THIS command system is hardwired into a specific processor.
Well, then everything is like a spool of threads, we place all sorts of connections for memory and given that there are millions of transistors in the processor, and let's say the "NOT" element contains 2 transistors, it's clear how many of these "cubes" are in the processor.
PS But to be honest, it doesn’t make sense to delve into these wilds of rational sense, since in Assembly there is 1 command, for example, in a 32-bit processor, let’s say 3 words of 4 bytes, that is, 12 bytes, and let’s say a C ++ program after compilation takes 200 kilobytes, then writing 16,000 lines of code is a task for a true masochist. such tasks are done by the team and everyone still writes 1-2 thousand lines, then it is merged into a common project and then we get the Win10 OS, which takes 4 gigabytes of code, well, in general, an unimaginable amount of work.

Answer 2

I'm posting links for you to check out.
https://qna.habr.com/q/740575
https://ichip.ru/tekhnologii/kak-rabotaet-processo...
https://ru.wikipedia.org/wiki/Architecture_von_Neumann
https://ru. wikipedia.org/wiki/Arithmetic-logical...
https://ru.wikipedia.org/wiki/Control_device
(as far as I understand the question, the main gag is in understanding the CU in general and the command decoder in particular; it's all really complicated)
And some quotes:
https://www.ixbt.com/cpu/cpu-pedia.shtml

predecoder, predecoder - a preliminary decoder that separates several CISC commands from a portion into separate elements (see x86), using information from the length gauge. Commands can be prepared ahead of their further processing by the decoder, if there is a buffer before it.
ILD (instruction length decoder: command length decoder), length gauge - CISC command length determinant. On x86, the CPU parses their prefixes, opcodes, and modR/M bytes. In Intel CPUs, the length gauge is part of the pre-decoder, measuring lengths on the fly. On most AMD CPUs, it works with instructions as they are loaded from L2 to L1I, storing instruction byte markup in extra bits in L1I read by the predecoder when a chunk is loaded.
ID (instruction decoder: command decoder), decoder (decoder) - a set of blocks that convert commands into mops. In x86-CPU consists of several translators and one microsequencer (uop sequence generator) with ROM for microcode. Performs microfusion and macrofusion.
translator ("translator"), the translator is the part of the decoder that processes simple and frequent commands without the use of microcode. The Intel x86 CPU has 1-3 simple translators (1 less than the number of pipeline paths), each of which translates an instruction at 1 uop per clock, and 1 complex translator that translates the instruction at 1-4 uop per clock. As a rule, the number of uops generated by translators is not greater than the number of paths. Most AMD CPUs have 3-4 translators, each translating an instruction at 1-2 uop/clock. Macro-leaked commands are processed in pairs by any translator, but no more than one pair per clock.
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Answer 3

in general terms: he understands as described in the command system.
the processor did not receive the command, it read it from the first byte of memory.
if a byte (or several) matches the command, it will execute, etc.
if the command assumes some data, then the bytes following the command are considered data, not a
logic command, and the instruction set depends on the processor.