RISC microinstruction set of Intel processors?

Question

Processors

Good time of the day. As you know, intel processors are CISC processors with a RISC core. Repeatedly met statements regarding the increase in the number of microcommands with the introduction of a new architecture. But nowhere did I meet the description of this set. I am writing a report on research in which this list is needed, at least 5 years ago. Maybe someone from Habravchan met a similar list?

Answer 1

And you are unlikely to meet. Intel deliberately hides the description of the microcode: firstly, so that it can be easily changed, and secondly, in order to hide details of the internal structure of the processor from competitors.
Here in this document:
Instruction tables
there is information about how many u-ops x86 instructions take. There is much more to this document.

Answer 2

>> As you know, intel processors are CISC processors with a RISC core.
Know where?
This is not true.
The microinstructions that are used there do not meet any of the criteria for RISC-ness.
Most x86 load-op commands are translated into 1 MOP.
Some more complex ones are broken. Rare and very complex ones are executed by microcode.
A specific set of microinstructions is not standardized in any way, because depends on the current processor microarchitecture.

Answer 3

en.intel.com/galaxy/forum/index.php?automodule=blog&blogid=5031
software.intel.com/en-us/articles/spiribit_article_1/
etc. google intel.com for "risc cisc"