Is it possible to organize such interfaces as HDMI or at least VGA on Altera Max 2?

Question

HDMI

The task is as follows: we receive video via HDMI (for example, from a laptop), divide each frame into two parts and send them to two monitors. Will there be enough CPLD Max 2 resources (now only one is available) for such an implementation?
And, if possible, please suggest video tutorials for a good start, which are not limited to Hello World with LED blinking. Grateful in advance

Answer 1

HDMI is a high speed serial interface. It is realistic to implement it using modern (and not so) FPGAs that have high-speed transceivers (MGT) on board (for Xilinx - GTX, GTP). CPLDs do not have such resources.
VGA is much simpler, but there "color" is encoded by the signal level - more voltage, stronger color. FPGA and CPLD do not know how to generate signals of different voltages, only 0 or 1. VGAs are implemented using ADC / DAC (even the simplest ones, on resistor assemblies). Fitting the control of 1x ADC and 2x DAC into a CPLD will be difficult (probably impossible).
Most often VGA in FPGA are considered with intermediate storage of the frame "inside". In principle, when considering the task of splitting a frame into two, it does not need to be stored - you can immediately forward it further. Therefore, your task with CPLD is at least theoretically feasible. However, if for some reason you have to save the frame first (unequal ADC / DAC speeds, the desire to somehow modify the frame, rearrange them, etc.), then the task will immediately go to the FPGA area due to the presence of internal memory blocks. Better yet, use external RAM.
Unfortunately, I can't recommend videos.

Answer 2

If you follow the path of Altera, then there are books on tutorials by Pong Chu, there are many practical examples and explanations