Is it possible to connect DDR2 in dual channel mode to FPGA?

Question

RAM

You need to make a board where the FPGA writes to memory and sends it over 10Gb Ethernet in parallel. The forwarded data stream is about 6 Gbps. The idea of ​​a dual-channel mode suggests itself - one module writes to memory, and the Ethernet module reads.
Question: are there IP cores that can dual-channel? If not, is it really possible to do this using two different modules for working with DDR2 (let's leave the question of the number of pins).
PS Do not suggest doing without memory, the buffer is required, and it can be very large (tens of GB).

Answer 1

Is quite real. You do not need a special ddr controller - you can get by with the standard ones and attach a stray with arbitration to it, which will write / read alternately. Inside the stray, make an internal buffer for writing, sufficient for the rapid accumulation of data while it is being read in the other direction.
If we do it completely collectively - two independent ddr controllers that change places for reading / writing as the memory fills up.

Answer 2

This is commonly referred to as dual port memory. A very expensive pleasure.
It makes no sense that you will have two modules - after all, the data from one must somehow get into the other!
Another thing is if you create one memory array using two modules, but you will write and read from them in turn - while one module performs a read / write operation, another one is being called ... Yes, and you don’t have to skip regeneration cycles.

Answer 3

I thought about something, and suddenly a brilliant idea came to my mind. To speed up performance, you just need to use modules in parallel. One module - read / write 32 bits at a time and two modules allow you to write 64 bits at a time - and so on. It remains only to implement a buffer that would accumulate 64 bits and write to such memory. When reading - 64 bits were read and given as needed, then we read the next portion.