How to ensure data integrity in EEPROM memory and FLASH memory with page erasure?

Question

Electronics

Good afternoon!

There was a data integrity issue when storing data in memory with paged erasure.
Memory AT45DB321.

In particular, there is a device that has many data structures stored in memory. These structures are not related to each other in any way, they can be changed randomly from the server, new ones can be added, old ones can be deactivated.
And here I thought about how to deal with a potential situation:
- a notification arrived that it was necessary to replace the STRUCT_N structure, which is located in the middle of the MEM_PAGE_X memory page,
- I start the process of rewriting the page (either by reading the page into RAM and replacing the data I need, or internal means of the microcircuit),
- during the overwriting process, a power failure occurred, it disappeared (either after erasing, or when the data began to be loaded into memory),
- after power was restored, I get a situation that, in addition to the current edited structure, I also suffered structures located on the same page as editable structure. Yes, I did not receive a response from the device that the structure being edited was changed and I will repeat this operation. But what about the rest of the data?

The problem is complicated by the fact that the server has absolutely no information about memory fragmentation, on which pages which structures are stored, etc. i have no idea exactly what structures i lost along with the edited structure.

Please advise what steps can be taken to avoid this?

One of the options that I see (not the most interesting solution for me):
- form data blocks directly on the server (with checksums),
- in case of any changes, the data on the server is first edited, the checksum is recalculated,
- after that it is sent the modification command to the device and in the response should come the checksum of the device's memory block,
- if it matches, then everything is OK, if it doesn't match, we load the full block of code from the server to the device.

However, this results in a too strong server-device connection, i.e. if I switched to another memory structure or another chip with a different block page size, then I need to make changes to the operation algorithm on the server.

Although, on the other hand, this will simplify the task of periodic data integrity monitoring, i.e. once in the N-th period of time, the server asks for memory checksums and checks with its own data.
Is it worth bothering with this?

Answer 1

Do you need EEPROM at all if you have a connection to the server?

You have two options - to solve the problem in hardware by hanging a capacitor and making external power control.
Or by writing a cunning storage system like a journaled fs, which will check the structure of blocks at startup and, using a through checksum, identify a block that was underwritten. It is clear that delivering all this to the protocol of communication with the server is a worthless idea, the device must monitor its memory itself.

Answer 2

Your problem is one: "- during the rewriting process, a power failure occurred, it disappeared."
This is a purely hardware issue at the level of the correctness of the chosen structure of the designed product.
If the hardware designer did not provide a way to "tell" the software about power problems and/or did not
take measures to protect against power loss at the design stage, then your attempts to fix it
in software are unlikely to be successful.

Answer 3

Plus for solving the problem at the hardware level, depending on the maximum duration of the rewriting process, choose a buffer power supply.