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How to boot Extreme x670-48x into backup BootRom?
Hello, I have an Extreme x670-48x switch that refuses to boot.
Outputs to the console:
Extreme Networks
Alternate BootStrap Image
Starting CRC of Default image
************************************************
* WARNING: Default BootLoader image is corrupt *
* Default BootLoader needs to be reinstalled *
************************************************
Processor ID = 000c8801
Set up DRAM
Aabcdefghijklmnopq1rEv
Memsize = 40000000
DRAM Post
Testing Dram
Running DRAM mats
DRAM mats Passed
SDRAM Memory setup complete.
Copy BootROM to execute location...
start = 9fc00000
copytoram = 9fc0c620
s0 = 1fbf0000
Copy BootROM to execute location done.
MSIZ
CPUF
RELS
RELC
DBGI
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if you have access to the console
You can view the software on the switch by issuing the show switch command. To select a
boot
partition
(for example, to download new software to the secondary
partition
), you need to run the command: use image secondary ways
if there are questions about extreme sports, then my skype is johnsn123
I know how to update software from BootROM, the problem is that it is broken and there is no access to the console. The same Concepts Guide describes how to load a BD from a backup BootROM, but for younger models this is not possible, although, as I already wrote, in the flash dump, which I made earlier from debug-mode, there are two copies of BootROM. I just hoped that there might be some kind of jumper to load a backup boot.
Z.Y. no one knows where to get the description of the processor? It is defined like this:
/exos/bin # cat /proc/cpuinfo
system type : RMI XLS Unknown A1
processor : 0
cpu model : RMI Phoenix V0.1
BogoMIPS : 658.63
wait instruction : no
microsecond timers : yes
tlb_entries : 64
extra interrupt vector : yes
hardware watchpoint : yes, count: 1, address/irw mask: [0x0fff]
ASEs implemented :
shadow register sets : 1
core : 0
VCED exceptions : not available
VCEI exceptions : not available
processor : 1
cpu model : RMI Phoenix V0.1
BogoMIPS : 658.63
wait instruction : no
microsecond timers : yes
tlb_entries : 64
extra interrupt vector : yes
hardware watchpoint : yes, count: 1, address/irw mask: [0x0fff]
ASEs implemented :
shadow register sets : 1
core : 1
VCED exceptions : not available
VCEI exceptions : not available
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