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How can FPGA parse Ethernet frames?
Good afternoon!
There was a following question. There is a debug board for Altera Cyclone IV, Arduino Mega and Raspberry Pi.
The task is to create a transparent (without its own IP address) device that would perform the following functions: receive an ethernet frame, deencapsulate and change its contents, pack it back into an ethernet frame and send it further to the recipient.
So far I’m thinking this way: is it possible to somehow raise the reception / transmission of data on Raspberry, then send them to the FPGA, process them there (suppose to encrypt), then return them to Raspberry and send them further over the network.
Physically, it looks like a "cut" of the UTP wire, into which my device is connected.
It is most likely possible to create such a device without using Raspberry or Arduino, but I would like to reduce the amount of additional circuitry, and I think that Raspberry or Arduino can help with this.
Thanks for any help.
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You need to start by linking technical parameters. What is the speed of Ethernet? 100? 1000?
What interfaces are on the development board?
What interfaces are there on the Rpi?
Will it be possible to organize a two-way channel of sufficient bandwidth between the RPI and the FPGA?
Will the FPGA be able to burst Ethernet frames on a stream by clock frequency?
The main question - what for here FPGA, when all this can be done (and for sure, everything has already been done) on a traditional machine? Exercise?
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