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10pnuk2020-06-03 05:02:42
RAM
10pnuk, 2020-06-03 05:02:42

Why do some RAMs have 3 timings and others 4?

Hello, why is there a description of three timings on some RAMs, and four on others? What does this mean, and which is better? Somewhere in general one timing.
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CityCat4, 2020-06-03
@CityCat4

In fact, there are about eight timings, but the first four usually matter for memory selection:
CL (CAS Latency) - time in bus cycles between the Column Access Strobe signal (addressing the column) and the actual start of reading data from it, in fact - the delay between the read command from memory and its actual beginning. The most important parameter, if one number is specified, is it. Less is better.
TRCD (RAS to CAS Delay) - time in bus cycles between the Row Access Strobe (row address) and Column Access Strobe (column address) signals, in fact - the delay between the row activation command and the read command from it (read delay - CL, that is reading from an inactive line will take time TRCD + CL). Less is better.
TRP (Row Precharge Delay) - time in bus cycles between the Precharge signal (close the line) and Row Access Strobe (open another line), in fact, the delay when switching memory lines (that is, if the Precharge command is received, the next read / write operation will not start earlier than through TRP + TRCD + CL). Less is better.
TRAS (Active To Prechagre Delay) - the time in bus cycles between the Row Access Strobe signal (open the line) and Precharge (close the line), in fact - the time of the operation with the line (memory will be able to switch to the operation with another line no earlier than this time). Less is better.
If instead of the approximate sum of the first three numbers, the number 1 or 2 is indicated, this is the Command Rate - the duration in cycles of any command.

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