State machine on HDL. Practical advice?

Question

Programming

Where to read the rules / tips for designing a spacecraft on HDL?
At the moment I am writing like this (controller for two DACs DAC121S101):

module DA2_controller
(
  input					clk,
  input					rst,
  input					start,
  input			[15:0] 	dA,
  input			[15:0]	dB,
  output reg				chA,
  output reg				chB,
  output reg				sclk,
  output reg				nsync,
  output reg				done
);

  localparam [1:0]  IDLE  	= 0,
              POS_CLK 	= 1,
              NEG_CLK	= 2;
              
  reg [1:0] state_reg, next_state;
  reg dchA, dchB;
  reg dsclk, dnsync;
  reg ddone;
  
  reg [15:0] dataA, dataB;
  reg [3:0] counter;
  
  always @(posedge clk)
    if (rst)
      begin
        state_reg <= IDLE;
        
        chA	<= 0;
        chB	<= 0;
        sclk	<= 0;
        nsync	<= 0;
        done	<= 1;
      end
    else
      begin
        state_reg <= next_state;
        
        chA	<= dchA;
        chB	<= dchB;
        sclk	<= dsclk;
        nsync <= dnsync;
        done	<=	ddone;
      end
      
  always @*
    begin
      dchA		= chA;
      dchB		= chB;
      dsclk		= sclk;
      dnsync	= nsync;
      ddone		= done;
      
      next_state = state_reg;
      
      case (state_reg)
        IDLE:
          if (start) 
            begin
              dataA 	= dA;
              dataB		= dB;
              ddone		= 0;
              dsclk		= 1;
              dnsync	= 1;
              counter 	= 15;
                            
              next_state = NEG_CLK;
            end
        POS_CLK:
          begin
            dsclk		= 1;
            dnsync	= 0;
            dchA		= dataA[counter];
            dchB		= dataB[counter];
            
            next_state = NEG_CLK;
          end
        NEG_CLK:
          begin
            dsclk	= 0;
            if (dnsync == 1)
              next_state = POS_CLK;
            else
              if (counter == 0)
                begin
                  ddone		  = 1;
                  next_state = IDLE;
                end
              else
                begin
                  counter 		= counter - 1;
                  next_state	= POS_CLK;
                end
          end
      endcase
    end
endmodule

What do you think?

Answer 1

Harris "digital circuitry and computer architecture"
I understand correctly what you did in the description of the synchronous reset?