Register initialization. Side effects?

Question

Programming

1. reg[2:0] a = 3'b100;
2. reg [2:0] a;
always @(posedge clk)
if(rst)
a = 3'b100;
else
begin
//
end
Yes, I understand that option #2 has an additional reset signal. But the question is: what could be the side effects (differences in behavior) in the case of using option #1 or #2?

Answer 1

Both options are synthesizable. Option 1:
Flashed (power on) - the register was set to "100", changed somehow, they wanted to return to the original state - but there is no setting signal! It will store the last modified value until the power is turned off.
Option 2:
Flashed (power on) - the register was set to "100", changed somehow, they wanted to return to its original state - they pulled rst!
In synthesis, it will give different constructions - option 1, it will probably be faster and less resource-intensive than option 2.
By the way, in the ISE Xilinx simulator, option 2 will give an indeterminate state on startup before explicitly submitting rst = 1. In VHDL, I combine both options at the beginning I define register with the initial value, and in the process I use the reset (set) signal.

Answer 2

what are the possible side effects

1st option: there will be a so-called. synthesis-simulation mismatch, because according to LRM (and in most correct CAEs) this construction is not synthesized

Answer 3

In case 2, an explicit reset occurs on the rising edge of the clock when the reset signal is present.
In case 1 - right after the description.