Programming taking into account ALU on asma and max load?

Question

Programming

Good day
to all, lately the idea to write an ultra-productive application has been coming to my mind more and more often, I usually write programs that are far from performance. and then the other day I read an article on a hacker https://xakep.ru/2013/02/19/60145/
I decided to write everything! no security! no multi-platform! no modularity! no users!
just me! just what you need! only my hardvar! the rest is redundant!
and more specifically, where can I read something like that, as well as about the ALU scheduler, and my processor architecture (how many dumps and sizes of any instruction caches) ?, Hyper-threading is also interested in, in particular
, if you use the same commands on 2 virtual cores one physical, will there be an acceleration?
my laptop: msi gt72 2qd dominator proc: intel i7-5700HQ(4:8 cores 2.7GHz 6mb-L3) while vidyuhu and related calculations are not affected.
I know more or less asm, and f, t, m - it doesn’t matter, the scheme is already clear to me

Answer 1

where to read? in the datasheet for the processor. but you probably won’t find a complete datasheet for i7, because they are usually distributed under NDA.
practice for example on arms, in phones / tablets. at least they have docks in full. search arm.com

Answer 2

look for datasheets for processors, do your tests
on the example of amd
developer.amd.com/resources/documentation-articles...
in addition to the ALU and FPU blocks described in the article, there is an address block, it can also be abused using lea
and of course get ready for the fact that 1 code must be rewritten a number of times, depending on the available instruction sets, as a minimum and as a maximum for each architecture