How to clock stm32 from external quartz?

Question

Microcontrollers

Digging through articles and Google, I wrote such a code for verification. But the LED does not even light up, there is an external quartz at 8 MHz, the STM32F103VCT6 controller.
CoIDE v2.0.2

#include "stm32f10x_gpio.h"
#include "stm32f10x_rcc.h"
#include "misc.h"

void delay(void) {
  volatile uint32_t i;
  for(i = 1; i != 0xFFFFF; i++);
}


int main(void) {
  RCC->CR |= RCC_CR_HSEON; // Запустить HSE
  while((RCC->CR & RCC_CR_HSERDY) == 0); // Ожидание готовности HSE
  RCC->CFGR |= RCC_CFGR_HPRE_DIV1 | RCC_CFGR_PPRE2_DIV1 | RCC_CFGR_PPRE1_DIV1; // HCLK = SYSCLK ;  PCLK2 = HCLK ; PCLK1 = HCLK
  RCC->CFGR &= ~((RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); // Предочистка
  RCC->CFGR |= RCC_CFGR_PLLSRC_HSE; // Тактировать PLL от HSE (8 MHz)
  RCC->CFGR |= RCC_CFGR_PLLMULL9; // Умножать частоту на 9 (8*9=72 MHz)
  RCC->CR |= RCC_CR_PLLON; // Запустить PLL
  while((RCC->CR & RCC_CR_PLLRDY) == 0); // Ожидание готовности PLL
  RCC->CFGR &= ~RCC_CFGR_SW; // Очистить биты SW0, SW1
  RCC->CFGR |= RCC_CFGR_SW_PLL; // Тактирование с выхода PLL
  while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1); // Ожидание переключения на PLL

  FLASH->ACR |= FLASH_ACR_PRFTBE; // Включить Prefetch Buffer
  FLASH->ACR &= ~(FLASH_ACR_LATENCY); // Предочистка
  FLASH->ACR |= FLASH_ACR_LATENCY_2; // Пропускать 2 такта

  // Настраиваем порт С
  GPIO_InitTypeDef PORT_C;
  RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOC, ENABLE);
  PORT_C.GPIO_Pin = (GPIO_Pin_9 | GPIO_Pin_8);
  PORT_C.GPIO_Mode = GPIO_Mode_Out_PP;
  PORT_C.GPIO_Speed = GPIO_Speed_2MHz;
  GPIO_Init(GPIOC, &PORT_C);


  while(1) {
    GPIOC->ODR |= (GPIO_Pin_8);
    delay();
    GPIOC->ODR &= ~(GPIO_Pin_8);
    delay();
  }
};

Answer 1

Weird. It started up fine for me.
Try reconfiguring the Flash memory BEFORE changing the main clock.
I remember that at a high operating frequency, the data simply cannot get out.
Everything else in the code seems to be in order.
If you are working in a debugger, you can follow the instructions somewhere after:
RCC->CR |= RCC_CR_PLLON; // Run the PLL
And see exactly where the problem is.
By the way, you can either move the lines
RCC->CFGR &= ~RCC_CFGR_SW; // Clear bits SW0, SW1
RCC->CFGR |= RCC_CFGR_SW_PLL; // Clocking from PLL output
while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_1); // Wait for switch to PLL
immediately after flash->acr