Is it possible to use string functions in specifying dependencies for targets?

Question

GNU Make

There was such a question.
Let's say there is a file src/Test/Test.cpp. After compilation, I want to get src_Test_Test.o.
Previously, in the makefile, I get the final name of the objects.
To return to the full name (with directory names) I write the following thing:

%.o : $(subst _,/,%.cpp)
     <...>

Actually the question is: is it possible to do this at all? It's just make that says no.
Or are there alternatives to this?

Answer 1

And I answer again.
No.