Is it possible to handle interrupts without TSS?

Question

assembler

I would like to know if it is possible to handle interrupts without defining the TSS descriptor in the GDT and setting its index to TR (x86_64)? Those. if you do not use IST, and the code and handler are in the zero ring (stack switching does not occur, red-zone is ignored). For a couple of days I've been trying to call the handler on the zero vector (divide by zero), but nothing happens. Is this fundamentally possible without TSS, its GDT descriptor, and setting it to TR? Or is one TSS necessary anyway? Thank you very much and Happy Holidays!

Answer 1

And I seem to have succeeded without TSS. Code here: github.com/jcmvbkbc/multiboot-tests

Answer 2

For a task-gate descriptor, TSS is of course required.
But the usual interrupt-gate, as far as I remember, do not have references to TSS.