How to design cycle failure indicator PCM-30(On ActiveHDL)?

Question

Software design

Good afternoon, I want to ask you how to simulate the cycle failure indicator in the VHDL language in the ActiveHDL program. The input is: D-data 1 \ 0, f0 the label of the cycle and frame synchronization. The output signals are AIS and LOF.

As far as I understand, when f0 is the cycle mark and f2m is the frame synchronization, then everything is fine, if one of them does not come, then we send units to the AIS output.
If at the input D: 1, then everything is fine, if 0, then what are we sending to the LOF input?

And how to write a program to manage all this?