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EEPROM resource saving algorithm when writing counters?
I am developing an amateur device in which there will be a counter with sequential values written to the EEPROM of the ATtiny13 controller. The manufacturer guarantees 100,000 rewrite cycles, I may have more.
The question is the following - imagine a 16-bit, for example, counter. When counting from 0000 to FFFF, the low bit will switch 65536 times, and the high bit will switch only twice! Those. cell wear is very uneven.
Is there an algorithm to encode the counter values in such a way that the bits wear out evenly? If not, perhaps it would be worth developing.
However, here a nuance arises - how is a byte written? Is it all erased and rewritten, or is it written bit by bit?
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I do not know what you are doing, but I would not use EEPROM like
that. There is RAM for this (which is not in ATtiny13, however). You can from time to time throw off the data in the EEPROM. In short, either change the MK or the algorithm. Alternatively, you can use an external EEPROM or SRAM.
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